The present invention relates to an improved memory cell organization and, more particularly, to an improved CMOS static RAM cell that provides improvements in functional performance while concurrently allowing higher-density integrated circuits.
In the design and fabrication of integrated circuits, one of the primary design imperatives is to increase functional density by decreasing feature size and packing more circuits closer together. As a consequence of more closely spaced circuit features, parasitic loading with the interconnect grids linking the circuits is commensurately reduced to improve circuit speed. Since power density increases with increased functional density, applied voltages and intra-circuit voltages have been decreased in order to address the heat dissipation problem associated with the increased functional density associated with smaller feature size and increased circuit packing.
The functional throughput rate is a figure of merit having units of gates-hertz per square centimeter. The functional throughput rate is essentially the product of the functional density (in gates per square centimeters) and the maximum circuit frequency (in hertz) and is used as a measure of the progress achieved in advanced microcircuit design and technology. Increased functional density, that is, obtaining the same function within a smaller chip area, is clearly the motivation driving attempts to design circuits to accomplish the same function with fewer transistors.
The present invention is directed to CMOS static RAM and is best appreciated in the context of the six transistor (6T) memory cell configuration of FIG. 1 and the five transistor (5T) configuration of FIG. 2.
FIG. 1 illustrates a standard 6T CMOS static RAM cell defined by MOS transistors TA, TB, TC, TD, TE, and TF; of these transistors, transistors TA and TB are PMOS transistors while the remaining transistors are of the NMOS type. Transistors TA and TC are serially connected between Vdd and ground to form a first inverter with a data node 1 between the two transistors, and, in a similar manner, transistors TB and TD are likewise connected between Vdd and ground to form a second inverter with a data node 2 therebetween. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. The transistor TE is connected between the bit line BL and the data node 1 to provide data access thereto, and the transistor TF is connected between the complementary bit line BLC and the data node 2 to similarly provide data access. The gates of the data access transistors TE and TF are connected to respective word lines WL; ancillary circuitry including differential-input sense amplifiers are not shown in FIG. 1.
The cross-coupled inverters of the 6T memory cell of FIG. 1 have two stable states functioning to store either a binary one or a binary zero. More specifically, the data access transistors TE and TF are gated into conduction by an appropriate voltage applied to the respective word lines while a binary high is impressed on data node 1 via the bit line BL and a binary low is impressed on the complementary bit line BLC. The transistor TD conducts to pull the data node 2 toward ground (binary low) while the data node 1 goes high. The opposite data state can be achieved by reversing the signals applied to the bit lines BL and BLC. The 6T memory cell of FIG. 1 is bi-directionally symmetrical, this is, currents, voltage levels, and time durations are the same for either stable state.
As is know in the art, an increase in functional density can be achieved by eliminating one data access transistor and eliminating the assoicated bit line. As shown in FIG. 2, the data access transistor TF and the bit line BLC have been eliminated to provide a five transistor (5T) configuration. Data to and from the 5T memory cell is controlled by gating the word line WL of the single access transistor TE to the single bit line BL and data node 1.
In contrast to the six transistor cell of FIG. 1 (which typically uses differential input sense amplifiers), the five transistor cell of FIG. 2 uses single-ended sense amplifers to read the status of data node 1. Prior to a data read, the bit line BL is initialized to a pre-determined voltage reference level (i.e., a mid-range voltage Vdd/2). The data access transistor TE is then turned-on by an appropriate voltage applied to its gate to access the voltage at data node 1 to allow the cell transistors to establish a difference or delta voltage on the bit line DL which is then read by the sense amplifier.
Unlike the six transistor cell of FIG. 1, the five transistor cell of FIG. 2 does not possess symmetry as between writing a binary one and a binary zero to the cell. More specifically, when writing a zero to the memory (that is, writing to the latches when the word line WL is active (i.e., high) and with the bit line BL driven low so that the zero state (data node 1 low and data node 2 high) is stored in the cell).
When effecting a zero write, the data access transistor TE is biased into its highly conductive ohmic or linear-mode (i.e., Vgsxe2x88x92VT greater than Vds) so that the conductive data access transistor TE can now sink any current that flows through the transistor TA and thereby drive the voltage at the data node 1 below the switching threshold of the inverter formed by TB and TD thus causing the latch to set in the zero state.
Conversely, when writing a one to the latch (that is, writing the latch when access transistor WL is active (high) and with the bit line BL driven high so that the one state (node 1 high and node 2 low) is stored in the latch) a condition occurs that can hinder driving the data node 1 sufficiently high to cause the desired switching. FIG. 3 is similar to FIG. 2 but shows (in bold line illustration) a voltage divider defined between the bit line BL, the data access transistor TE, the transistor TC, and ground with the data node 1 representing the mid-point of the voltage divider. When writing a one to the memory cell, the access transistor TE is operating in its highly resistive saturation-mode (i.e., VGSxe2x88x92VT less than VDS) and so the voltage divider formed by the transistor TE (in its saturation-mode) and the transistor TC (in its linear-mode) has difficulties driving the voltage at data node 1 high enough to exceed the switching threshold of the inverter formed by transistors TB and TD to cause the latch to set to the desired one state.
Various techniques have been developed to address this xe2x80x9cwrite onexe2x80x9d problem in 5T SRAM cells; each technique also generates specific drawbacks when addressing the xe2x80x9cwrite onexe2x80x9d problem including:
(a) bi-level word line clocking schemes have been used for gating the access transistor TE using a boosted word line WL voltage during the write operation so that the access transistor TE always operates in its linear-mode (i.e., in its ohmic or triode region);
(b) asymmetric cell designs that skew the switching thresholds of the inverters forming the latch to facilitate the write-one operation;
(c) multiple device threshold voltages or dynamic device threshold voltages used selectively within the SRAM cell design to enhance the write-one operation; and
(d) providing the access device with a significantly wider channel to compensate for the limited channel conductance of its saturation-mode operation.
Each of these options require either a more complicated device process, more complicated device design, or more complicated operational and clocking schemes, or a combination of each of these solutions. The use of a larger-channel access transistor is in a technical direction opposite from the very design precepts that favor the 5T cell design, viz., increased functional density.
In view of the above, it is an object of the present invention, among others, to provide a high-performance high-density CMOS SRAM cell.
It is another object of the present invention to provide a high-performance high-density CMOS SRAM cell having increased functional and operation density.
It is still another object of the present invention to provide a high-performance high-density 5T CMOS SRAM cell having increased functional and operation density.
In view of these objects, and others, the present invention provides a high-performance high-density CMOS SRAM cell having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors serially connected between Vdd and circuit ground to form a first inverter with a first data node between the two transistors, and, in a similar manner, to form a second inverter with a second data node therebetween. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor is connected between a bit line BL and the first data node to provide data access thereto. A diode is connected between the data node of one of the inverters and the common gate connection of the other inverter to facilitate the xe2x80x9cwrite onexe2x80x9d operation. The diode can be implemented in dual work function polysilicon topologies by selectively doping adjacent regions of the single gate level polysilicon with an appropriate polysilicon doping type and concentration for each transistor type to form PN junctions in the polysilicon. A window is formed in the silicide strapping layer to enable the PN junction operation.
The present invention provides a CMOS SRAM cell that provides the same performance as prior designs but with fewer transistors and with a smaller cell size for increased functional density.
Other objects and further scope of applicability of the present invention will become apparent from the detailed description to follow, taken in conjunction with the accompanying drawings, in which like parts are designated by like reference characters.